The present invention relates generally to memory devices and in particular the present invention relates to read data paths in a memory device.
Integrated circuit memory devices typically include one or more arrays of memory cells that store data. The data is either read from or written to the memory cell using data communication connections. Some example memory devices include but are not limited to random access memories (RAM), dynamic random access memories (DRAM), Synchronous DRAM (SDRAM), static RAM (SRAM), and non-volatile memories such as FLASH.
During production of the memory devices, the individual memory cells need to be tested. Thus, data is written to the memory cells and then the data is read from the memory. As the density of the memory arrays increase, the time needed to fully test the memory array also increases.
One technique that can be used to decrease test time is data compression. That is, data read from multiple memory cells are compressed into a smaller number of data bits. Thus, less data communication connections (DQ""s) are required for a given number of memory cells when implementing data compression. The data compression circuitry is included in the memory device and adds overhead to the data read and write paths. This overhead can decrease operating speeds during normal, non-test operations.
For the reasons stated above, and for other reasons stated below which will become apparent to those skilled in the art upon reading and understanding the present specification, there is a need in the art for a memory device having data compression circuitry while maintaining suitable operating speeds during normal, non-test operations
The above-mentioned problems with memories and other problems are addressed by the present invention and will be understood by reading and studying the following specification.
In one embodiment, a non-volatile flash memory device comprises an array of non-volatile memory cells, a plurality of data output buffers to provide data from the array to external nodes, and control circuitry to control perform test operations on the array and provide compressed output data.
In another embodiment, a memory device comprises a memory array with 4-banks of memory cells arranged in rows and columns, 16-output buffers coupled to the 4-banks to provide data on 16-output nodes, and a first set of data paths coupled between the 4-banks and the 16x-output buffers to couple data from 16-columns of one of the 4-banks to the 16-output buffers. A second set of data paths are coupled between the 4-banks and the 16-output buffers, the second set of data paths comprise compression logic to simultaneously couple 16-columns from the 4-banks to 4 of the 16-output buffers. The embodiment also includes multiplex circuitry coupled to the output buffers and the first and second sets of data paths to selectively couple the first or second data path to the output buffers.
A non-volatile flash memory device of one embodiment comprises an array of non-volatile memory cells, a plurality of data output buffers to provide data from the array to external nodes, and control circuitry to control perform test operations on the array and select an output data path including compression circuitry to provide compressed output data.
A method of operating a memory comprises initiating a test operation, and coupling data from the array to output connections through compression circuitry to provide compressed data.